Currently, almost all central processing units (CPUs) included in semiconductor devices adopt an architecture called a stored-program system. In this stored-program system, instructions to be processed by a CPU and data necessary for the processing are stored in a memory, and the CPU performs processing by sequentially reading data from the memory. Therefore, for the semiconductor device having a CPU, techniques for increasing an operating frequency of CPU and increasing a memory access rate are employed in order to improve performance.
The semiconductor device can have higher arithmetic processing performance by increasing the operating frequency of the CPU. However, the amount of electric power consumed by the semiconductor device is increased in proportion to the operating frequency. In addition, an increase in operating frequency generally requires an increase in circuit size of the CPU. Thus, the CPU consumes more power as the operating frequency is increased. Therefore, there has been proposed a system for improving overall processing performance of a semiconductor device by providing a plurality of CPUs which consume less power due to suppressed circuit size and operating frequency and by distributing processes to all of the CPUs (for example, Reference 1: Japanese Published Patent Application No. 2006-268070). Such a system may be referred to as a multi-core system.
As the multi-core system, various structures and data processing methods have been proposed, such as a symmetric multiprocessing (SMP) system where CPUs are treated equally, an asymmetric multiprocessing (AMP) system where CPUs are treated unequally, a single instruction multiple data (SIMD) method in which plural pieces of data are processed with a single instruction, and a multiple instruction multiple data (MIMD) method in which plural pieces of data are processed with plural instructions. The multi-core system can reduce power consumption of each CPU.